The present invention relates to a method of joining composite structures, and, more particularly, to a joining method suitable for hermetic sealing of a package having narrow sealing surfaces.
Semiconductor devices such as IC, LSI and so on are received in sealed packages charged with an inactive gas for the purpose of protecting the devices from the atmosphere. Examples of sealing packages are respectively disclosed in Japanese Patent Unexamined Publication (Tokkaisho) No. 51-15973 and No. 61-29155. In Japanese Patent Unexamined Publication No. 51-15973, each of the metal foundation films, respectively provided as wiring films on sealing planes provided for seal-joining the external structural members of a package together, is divided into a plurality of separated zones. A solder film, interposed as a sealing material between the opposite metal foundation films, is also divided to correspond with the plurality of zones of the metal foundation film. Undesirable voids produced in the soldering film are therefore also divided into portions of a small volume. If the solder film is not divided into a plurality of zones, a single large void occurs in the soldering film, resulting in a reduction in the hermetic sealing performance.
In Japanese Patent Unexamined Publication No. 61-29155, many through holes or small grooves are formed in the sealing plane over the entire periphery of a cap, which is one of the external constitutive members of a package. Such through holes or small grooves open the voids produced in the solder film provided on the sealing plane and thus allow gases in the voids to escape enabling a manufacturing of products without any voids and bringing about an improvement in the hermetic sealing effect.
A common problem of the above-described techniques is particularly prevalent in applications in which the width of each of the sealing planes is reduced. There is a demand for a reduction in the width of each of the sealing planes in a small package in which a large-scale integrated circuit chip used for a high speed computer is sealed. A reason for this is that high density packing in which many small packages are mounted adjacent to each other on one wiring board leads to a reduction in the speed of electrical signals due to the fact that the wiring length, which corresponds to the thickness of the package side wall being equal to the width of each sealing surface, is added to the wiring length between respective chips. In addition, complicated processing must be performed in the portions of the sealing planes of chips designed for such applications. Thus, the above-described prior art cannot be easily realized when the size of a package is reduced to the size of a chip.